1) Field of the Invention
The present invention relates to a semiconductor memory device which has an error-correction function (for correcting defective bits) and a burst-mode function.
2) Description of the Related Art
The semiconductor memory devices having the burst-mode function are known (for example, as disclosed in Japanese Unexamined Patent Publication No. 4-291084). According to the burst-mode function, a plurality of data pieces are transferred together in response to one operation of designating addresses of a memory core so that the data transfer rate is increased.
FIG. 15 is a timing diagram of signals in a burst-mode (write) operation performed in a conventional semiconductor memory device in the case where the start address is A(1). In the example of FIG. 15, the write latency (WL) is two, and the burst length (BL) is eight. When the start address is inputted, a word line corresponding to the start address is selected, a voltage difference occurs between the pair of bit lines b1 and b1b, and a sense operation is started. The address is sequentially incremented as A(1)→A(2)→A(3)→A(4)→A(5)→A(6)→A(7)→A(8), although the addresses A(2) to A(8) are not indicated in FIG. 15. While the address is changed as above, the word-line selection address w1 is not changed. The data pieces to be written (hereinafter referred to as write-data pieces) are captured in the order of W1(1)→W1(2)→W1(3)→W1(4)→W2(1)→W2(2)→W2(3)→W2(4). In this specification, it is assumed that the size of each data piece is 16 bits unless otherwise specified. The data pieces to be written are respectively outputted onto data buses being arranged between input terminals DQ and memory cells and having the total width of 64 bits, and the data pieces on the data buses are changed one after another as W1(1)→W2(1), W1(2)→W2(2), W1(3)→W2(3), and W1(4)→W2(4). The data pieces outputted onto the data buses and constituted by 64 bits are written in the memory cells in each of the two write cycles in which the address is A(4) and A(8), respectively. The timings of the address increment and the data capture are synchronized with the clock signal CLK. The data pieces W1(1) to W1(4) are written in the memory cells in the first write cycle (in which the address is A(4)). At this time, the column-selection signals CL1(1) to CL1(4) are active. In addition, the data pieces W2(1) to W2(4) are written in the memory cells in the second write cycle (in which the address is A(8)). At this time, the column-selection signals CL2(1) to CL2(4) are active. The time interval (expressed by the number of clock cycles) from the clock timing in synchronization with which the final write cycle (the above write operation in the second write cycle in this example) is started, until the bit lines are equalized and the start of the next command (WR or RD) is enabled is called the write recovery time (tWRB).
The burst-mode operation may be started from another address (A(2), A(3), or A(4)) instead of A(1). Even in such a case, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are concurrently activated, and the following control operations are performed.
FIG. 16 is a timing diagram of signals in a burst-mode (write) operation performed in the conventional semiconductor memory device in the case where the start address is A(2).
In this case, the address is sequentially incremented as A(2)→A(3)→A(4)→A(5)→A(6)→A(7)→A(8)→A(1). While the address is changed as above, the word-line selection address w1 is not changed. The data pieces to be written are captured in the order of W1(2)→W1(3)→W1(4)→W2(1)→W2(2)→W2(3)→W2(4)→W1(1). The data pieces to be written are respectively outputted on data buses being arranged between the input terminals DQ and the memory cells and having the total width of 64 bits, and the data pieces on the data buses are changed one after another as W1(2)→W2(2), W1(3)→W2(3), W1(4)→W2(4), and W1(1)→W2(1). The data pieces outputted onto the data buses and constituted by 64 bits are written in the memory cells in each of the three write cycles in which the address is A(4), A(8), and A(1), respectively. The timings of the address increment and the data capture are synchronized with the clock signal CLK. The data pieces W1(2) to W1(4) are written in the memory cells in the first write cycle (in which the address is A(4)). At this time, although the column-selection signals CL1(1) to CL1(4) are active, the data piece W1(1) is masked and is not written in the memory cells. In addition, the data pieces W2(1) to W2(4) are written in the memory cells in the second write cycle (in which the address is A(8)). At this time, the column-selection signals CL2(1) to CL2(4) are active. Further, the data piece W1(1) is written in the memory cells in the third write cycle (in which the address is A(1)). At this time, although the column-selection signals CL1(1) to CL1(4) are active, the data pieces W1(2) to W1(4) are masked and are not written in the memory cells. That is, the same column-selection signals CL1(1) to CL1(4) are activated in the first and third write cycles. The write recovery times (tWRB) in the burst-mode (write) operations of FIGS. 15 and 16 are identical.
FIG. 17 is a timing diagram of signals in a burst-mode (write) operation performed in the conventional semiconductor memory device in the case where the start address is A(3).
In this case, the address is sequentially incremented as A(3)→A(4)→A(5)→A(6)→A(7)→A(8)→A(1)→A(2). While the address is changed as above, the word-line selection address w1 is not changed. The data pieces to be written are captured in the order of W1(3)→W1(4)→W2(1)→W2(2)→W2(3)→W2(4)→W1(1)→W1(2). The data pieces to be written are respectively outputted on data buses being arranged between the input terminals DQ and the memory cells and having the total width of 64 bits, and the data pieces on the data buses are changed one after another as W1(3)→W2(3), W1(4)→W2(4), W1(1)→W2(1), and W1(2)→W2(2). The data pieces outputted onto the data buses and constituted by 64 bits are written in the memory cells in each of the three write cycles in which the address is A(4), A(8), and A(2), respectively. The timings of the address increment and the data capture are synchronized with the clock signal CLK. The data pieces W1(3) and W1(4) are written in the memory cells in the first write cycle (in which the address is A(4)). At this time, although the column-selection signals CL1(1) to CL1(4) are active, the data pieces W1(1) and W1(2) are masked and are not written in the memory cells. In addition, the data pieces W2(1) to W2(4) are written in the memory cells in the second write cycle (in which the address is A(8)). At this time, the column-selection signals CL2(1) to CL2(4) are active. Further, the data pieces W1(1) and W1(2) are written in the memory cells in the third write cycle (in which the address is A(2)). At this time, although the column-selection signals CL1(1) to CL1(4) are active, the data pieces W1(2) to W1(4) are masked and are not written in the memory cells. That is, the same column-selection signals CL1(1) to CL1(4) are activated in the first and third write cycles. The write recovery times (tWRB) in the burst-mode (write) operations in the case of FIGS. 15, 16, and 17 are identical.
Since the above control operations are performed, the conventional semiconductor memory device having a burst-mode function can perform a burst-mode operation without reducing the operation speed even when the start address is changed.
Recently, the ECC (error checking and correcting) function is installed as a measure for coping with defects caused by abrupt variations in the holding times in the memory cells which require a refresh operation as in the memory cells in the DRAM (dynamic random access memory). For example, provision of such a function is disclosed in Japanese Unexamined Patent Publication No. 2002-56671.
The ECC function which can correct a single-bit error is widely used. In the case where such a function is used, even a single-bit error contained in data read out from the memory cells can be corrected. In the examples used in the following descriptions, Hamming codes as ECC codes are produced by using 64 data bits and seven parity bits.
FIG. 18 is a block diagram of first circuitry realizing an ECC function and a burst-mode function in a conventional semiconductor memory device. The conventional semiconductor memory device 800 of FIG. 18 comprises a syndrome generation circuit 801, a decoder 802, an error correction circuit 803, a data selection circuit 804, write-data holding circuits 805-1, 805-2, 805-3, and 805-4, write-status holding circuits 806-1, 806-2, 806-3, and 806-4, read/write data selection circuits 807-1, 807-2, 807-3, and 807-4, and a parity generation circuit 808. In FIG. 18, the memory cells are not indicated.
The syndrome generation circuit 801 generates a 7-bit syndrome signal S on the basis of data pieces r(1), r(2), r(3), and r(4) read out from the memory cells (hereinafter referred to as read-data pieces) and a set of seven parity bits P0, which are read out from the memory cells. Each of the read-data pieces r(1), r(2), r(3), and r(4) is constituted by 16 bits, and thus the total number of bits of the read-data pieces r(1), r(2), r(3), and r(4) is 64.
The decoder 802 decodes the syndrome signal S, and generates 64-bit error correction flags err. The error correction circuit 803 corrects (inverts) a bit of the read-data pieces r(1), r(2), r(3), and r(4) corresponding to one of the error correction flags err when the one of the error correction flags err is valid, and outputs corrected read-data pieces R(1), R(2), R(3), and R(4).
The data selection circuit 804 performs parallel-to-serial conversion of 64-bit data outputted from the memory cells, into 16-bit form for outputting the converted data through 16-bit I/O ports, in response to an output enable signal.
The write-data holding circuits 805-1, 805-2, 805-3, and 805-4 capture 16-bit write-data pieces (i.e., data to be written in the memory cells) from the I/O ports in turn in response to write enable signals WE1, WE2, WE3, and WE4, respectively, and hold the captured write-data pieces as write-data pieces W(1), W(2), W(3), and W(4). The write-status holding circuits 806-1, 806-2, 806-3, and 806-4 determine whether or not the captured write-data pieces is to be written in the memory cells, in response to a status initialization signal.
Each read/write data selection circuit 807-i determines one of the write-data piece W(i) and the corrected read-data piece R(i) as a data piece C (i) which is to be written in the memory cells, according to a signal outputted from the corresponding write-status holding circuit 806-i, and the parity generation circuit 808 receives the data piece C(i) determined by the read/write data selection circuit 807-i, generates a set of seven parity bits P on the basis of the received data piece C(i), and outputs the set of seven parity bits P, where 1≦i≦4.
In the following explanations, it is assumed that the burst length (BL) is eight, and the minimum unit of the write data (which is referred to as a write block or a word structure) is constituted by 16 bits. In this case, when the addresses A(1) to A(8) are supplied to the semiconductor memory device for the burst-mode operation, the 64-bit data corresponding to the four successive addresses A(1) to A(4), or A(5) to A(8) constitute the ECC code.
FIG. 19 is a timing diagram of signals in a burst-mode (write) operation performed in the conventional semiconductor memory device 800 (having the ECC function) in the case where the start address is A(1) and the write latency (WL) is two as in the case of FIG. 15. However, in the semiconductor memory device 800 having the ECC function, when data are written in the memory cells, it is necessary to read out read-data pieces r(1) to r(4) from the memory cells for generation of a set of parity bits. Hereinafter, this operation is referred to as an ECC-RD operation. It is assumed that the duration of the ECC-RD operation is shorter than the period of the clock signal.
When a word line is selected according to the start address, a voltage difference occurs between the pair of bit lines b1 and b1b, and a sense operation is started. At this time, in order to perform the ECC-RD operation, the duration in which a column-selection line in the memory cells is active is different from the corresponding duration in the case of FIG. 15. Regardless of the start address, at the times of the ECC-RD and write (WR) operations, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are active. Even after the ECC-RD operation is completed, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are maintained active. The write operations are performed in two write cycles in which the address is A(4) and A(8), respectively. In each write operation, the data pieces C(1), C(2), C(3), and C(4) selected by the read/write data selection circuits 807-1, 807-2, 807-3, and 807-4 and the set of parity bits P generated by the parity generation circuit 808 are written in the memory cells. The write-data pieces W1(1) to W1(4) are selected as the data pieces C(1) to C(4) in the first write cycle, and the write-data pieces W2(1) to W2(4) are selected as the data pieces C(1) to C(4) in the second write cycle. The four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) become inactive when the corresponding write operation is completed. In the case where the start address is A(1), the write recovery time (tWRB) is not changed even when the ECC operation is performed.
FIG. 20 is a timing diagram of signals in a burst-mode (write) operation performed in the conventional semiconductor memory device 800 (having the ECC function) in the case where the start address is A(2).
As in the case of FIG. 16, when a word line is selected according to the start address, a voltage difference occurs between the pair of bit lines b1 and b1b, and a sense operation is started. At this time, in order to perform the ECC-RD operation, the duration in which a column-selection line in the memory cells is active is different from the corresponding duration in the case of FIG. 16. At the times of the ECC-RD and write (WR) operations, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are active. Even after the ECC-RD operation is completed, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are maintained active. The write operations are performed in each of three write cycles in which the address is A(4), A(8), and A(1), respectively. In the first write cycle, in order to obtain a necessary number of data bits for generation of a set of parity bits P by the parity generation circuit 808, the corrected read-data piece R(1) (indicated in FIG. 18) which corresponds to the address A(1) and is read out and corrected by the ECC-RD operation and the write-data pieces W1(2) to W2(4) are selected and written as the data pieces C(1) to C(4), although the corrected read-data piece R(1) is not indicated in FIG. 20. In addition, the write-data pieces W2(1) to W2(4) are selected and written as the data pieces C(1) to C(4) in the second write cycle, and the write-data piece W1(1) is selected and written as the data piece C(1) in the third write cycle. Although the four column-selection signals CL1(1) to CL1(4) are active in the third write cycle, the write-data pieces W1(2) to W1(4) are masked and are not written in the memory cells. Instead, in order to obtain data bits necessary for generation of a set of parity bits P by the parity generation circuit 808, the corrected read-data pieces R(2) to R(4) read out and corrected by the ECC-RD operation are used as the write-data pieces W1(2) to W1(4). At this time, the read-data pieces R(2) to R(4) are the write-data pieces W1(2) to W1(4) which have been written by the first write cycle. Specifically, the read/write data selection circuit 807-1 selects and outputs the write-data piece W1(1), and the read/write data selection circuits 807-2, 807-3, and 807-4 select and output the corrected read-data pieces R(2) to R(4), according to the signals from the write-status holding circuits 806-1, 806-2, 806-3, and 806-4 illustrated in FIG. 18. The four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) become inactive when the corresponding write operation is completed. Further, the same column-selection signals CL1(1) to CL1(4) are activated in the first and third write cycles.
The operations in FIG. 20 are greatly different from the operations in FIG. 16 in the write operation at the address A(1) (i.e., in the third write cycle). That is, since, in the case where the start address is A(2), the ECC-RD operation and the write operation are successively performed, the timing of the equalization of the bit lines is delayed by the duration of the ECC-RD operation. Therefore, the write recovery time (tWRB) in the burst-mode operation of FIG. 20 in the semiconductor memory device 10a having the ECC function is greater than the write recovery time (tWRB) in the burst-mode operation of FIG. 16 in the semiconductor memory device without the ECC function by one cycle of the clock signal.
FIG. 21 is a timing diagram of signals in a burst-mode (write) operation performed in the conventional semiconductor memory device 800 (having the ECC function) in the case where the start address is A(3).
As in the case of FIG. 17, when a word line is selected according to the start address, a voltage difference occurs between the pair of bit lines b1 and b1b, and a sense operation is started. At this time, in order to perform the ECC-RD operation, the duration in which a column-selection line in the memory cells is active is different from the corresponding duration in the case of FIG. 17. At the times of the ECC-RD and write (WR) operations, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are active. Even after the ECC-RD operation is completed, the four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) are maintained active. The write operations are performed in three write cycles in which the address is A(4), A(8), and A(2), respectively. In the first write cycle, the corrected read-data pieces R(1) and R(2) (illustrated in FIG. 18) read out and corrected by the ECC-RD operation, and the write-data pieces W1(3) and W2(4) are selected and written as the data pieces C(1) to C(4), although the corrected read-data piece R(1) is not indicated in FIG. 20. In addition, the write-data pieces W2(1) to W2(4) are selected and written as the data pieces C(1) to C(4) in the second write cycle, and the write-data pieces W1(1) and W1(2) are selected and written as the data pieces C(1) and C(2) in the third write cycle. Although the four column-selection signals CL1(1) to CL1(4) are active in the third write cycle, the write-data pieces W1(3) and W1(4) are masked and are not written in the memory cells. Specifically, the read/write data selection circuits 807-1 and 807-2 select and output the write-data pieces W1(1) and W1(2) as the data pieces C(1) and C(2), and the read/write data selection circuits 807-3 and 807-4 select and output the corrected read-data pieces R(3) and R(4) as the data pieces C(3) and C(4), according to the signals from the write-status holding circuits 806-1, 806-2, 806-3, and 806-4 illustrated in FIG. 18. At this time, the read-data pieces R(3) and R(4) are the write-data pieces W1(3) and W1(4) which have been written by the first write cycle. The four column-selection signals CL1(1) to CL1(4) or the four column-selection signals CL2(1) to CL2(4) become inactive when the corresponding write operation is completed. Further, the same column-selection signals CL1(1) to CL1(4) are activated in the first and third write cycles.
The operations in FIG. 21 are greatly different from the operations in FIG. 17 in the write operation at the address A(2) (i.e., in the third write cycle). Although the ECC-RD operation and the write operation are successively performed in a similar manner to the case of FIG. 20 where the start address is A(2), the ECC-RD operation in the case of FIG. 21 where the start address is A(3) is completed before the write operation at the address A(2). Therefore, the duration of the equalization of the bit lines does not trespass on the time for the subsequent operations. Thus, the write recovery time (tWRB) is unaffected by the existence or absence of the ECC function. Although not explained, the write recovery time (tWRB) is also unaffected by the existence or absence of the ECC function in the case where the start address is A(4).
As explained above, in the conventional semiconductor memory device having the ECC function and the burst-mode function, the write recovery time increases depending on the start address (as in the case where the start address is A(2)).